In transmission arrangements, for example for mobile radio, a modulation signal firstly needs to be modulated onto a radio-frequency carrier and secondly the carrier frequency needs to be stabilized and adjustable.
One possible way of doing this is provided by a phase locked loop, a PLL, which is firstly used as a frequency synthesizer and secondly has the modulation signal introduced into it. The modulation signal can be fed in at different points in the PLL, with an implicit high-pass filter or low-pass filter response being obtained on the basis of the connection point for the modulation signal.
The document DE 199 29 167 specifies a modulator and a method for phase or frequency modulation with a PLL circuit, where the modulation signal is introduced at a point in the PLL at which a high-pass filter response is obtained for the modulation frequency, and at the same time is introduced at a further point in the PLL, at which a low-pass filter response is obtained. Such a modulator is also referred to as a two-point modulator. Normally, the modulation signal is impressed on the input of the oscillator in the PLL in digital form, by varying the division ratio for the frequency divider in the PLL, and at the same time in analog form.
A fundamental advantage of such two-point modulation is that the bandwidth of the control loop can be designed to be much smaller than transfer of the modulated data actually requires. This results in advantages in terms of the noise response. In addition, in contrast to “open loop” designs, in which the control loop is opened as soon as the PLL has locked onto the desired carrier frequency, the control loop may also remain closed during the modulation.
Besides purely digital modulation over the variation in the division ratio of the frequency divider with a small bandwidth, the two-point modulator design involves the analog modulation at the oscillator input being used to compensate for the limited bandwidth.
In the case of the two-point modulation, particular attention needs to be paid to phase equality for the analog and digital modulation data which are fed into the PLL. In addition, it is necessary to ensure a good match between the amplitudes of the two modulation signals.
Drawbacks of the two-point modulator design become apparent, however, when this design is intended to be used in “multiple clock” systems. Such systems occur in modern mobile radio systems, for example in “dual band” or “triband” appliances and also in multimode appliances. These appliances can be operated either in various frequency bands or even using various mobile radio standards, such as GSM (Global System for Mobile Communication), and UMTS (Universal Mobile Telecommunication Standard).
The modulation data to be transmitted are normally conditioned in a digital signal processor, which may comprise blocks for protocol processing and one or more processors, for example. The output signal from the digital signal processor is normally routed via a digital filter which performs any signal shaping which is required for the bits that are to be transmitted, for example Gaussian filtering in the case of Gaussian frequency shift keying. The output data from the digital filter may be routed to the frequency divider via a digital sigma-delta modulator, for example, which means that a fractional rational division ratio is obtained on average over time. In addition, the digital modulation signal is routed to the input of the controlled oscillator in the PLL via an analog filter, a digital/analog converter or the like in the form of an analog modulation signal.
The digital signal processor and the digital filter at the output of the signal processor are normally designed for a particular clock frequency. This clock frequency firstly stipulates the timing for the protocol sequence, but secondly stipulates the response of the digital filter as well. For the purpose of pulse shaping in the digital filter, a particular ratio between the bit clock and the clock frequency of the digital signal processor is assumed, for example, and in line with this ratio, by way of example, a “state machine” is implemented in the signal processor, which state machine outputs the respective amplitude values of the modulation signal to be transmitted for the various changes in the digital clock.
The digital sigma-delta modulator also effects “noise shaping”, i.e. shifts all of the noise in a distribution over the frequency range and into uncritical ranges. The output signal from the sigma-delta modulator is routed to the frequency divider in the radio-frequency PLL and hence is subjected to low-pass filtering implicitly in relation to the radio-frequency output on the oscillator in the PLL. In this scenario, the sigma-delta modulator is operated at the same reference frequency as is also used as the reference frequency for the PLL, to be more precise for the phase comparator or phase detector.
For this constant reference frequency, which serves as reference frequency for the PLL and also as clock frequency for the digital signal processor, including the digital filter, the overall system is produced permanently once. If the PLL is intended to be operated at various reference frequencies, however, for example in a multiple clock system as explained above, then the problem arises that the clock frequency needs to be constant for the digital signal processor nevertheless so that the time base for the protocol processing does not change at various reference frequencies.
This could be done, by way of example, by virtue of a further synthesizer being provided which derives the clock frequency for the digital signal processor from the reference frequency and always provides a constant clock frequency regardless of a varying reference frequency.
On account of the spectral purity demanded, the PLL itself which forms the two-point modulator needs to be operated directly at the reference frequency, however. It is thus also necessary to operate any digital sigma-delta modulator provided at this reference frequency.
What is problematical is therefore transferring the modulation data from the digital signal processor, which needs to be operated at a constant frequency, to the digital sigma-delta modulator or to the frequency divider in the radio-frequency PLL, which in turn need to be operated at a variable reference frequency.